I am Wenyong Zhou, and I earned my PhD from the University of Hong Kong (HKU) under the supervision of Prof. Ngai Wong and Prof. Can Li. My research lies at the intersection of AI systems, computer architecture, and emerging hardware.

My goal is to make increasingly capable AI efficient, reliable, and deployable in the real world. I pursue this goal through cross-layer co-design, jointly rethinking computing platforms, model representations, runtime mechanisms, and generation algorithms. Rather than treating hardware and AI models as independently optimized layers, I study how their interactions shape the end-to-end cost, performance, and reliability of modern AI systems.

A central focus of my work is memory-centric and analog compute-in-memory hardware, which offers a promising path toward reducing data movement but also introduces constraints in precision, data conversion, noise, and device variability. I use these emerging platforms as both a key opportunity and a demanding testbed for developing general principles of hardware-aware, workload-aware, and reliability-aware AI system design.

Research Interests

My research develops efficient and reliable AI systems through cross-layer co-design across hardware, models, and runtime software. I am particularly interested in:

• Efficient AI Computing Platforms
  Memory-centric architectures, emerging hardware, heterogeneous systems, and design methodologies that reduce data movement and improve the end-to-end efficiency of AI workloads.

• Hardware-Aware Model Representation and Adaptation
  Quantization, precision allocation, efficient fine-tuning, and model representations that adapt to the cost, fidelity, and resource constraints of target hardware.

• Foundation-Model Execution and Generation
  Algorithms and runtime systems for efficient long-context processing, KV-cache management, decoding acceleration, and alternative generation paradigms.

• Reliable AI under Approximation and Hardware Imperfections
  Cross-layer techniques that enable robust and trustworthy model behavior under low precision, approximate computation, analog noise, device variation, and dynamic system effects.

Recent News

• 2026.09 - Seven papers were accepted by ASPDAC 2027.
• 2026.08 - Two papers were accepted by ICCD 2026.
• 2026.04 - One paper was accepted by IEEE TC.
• 2026.02 - One paper was accepted by DAC 2026.
• 2026.02 - One paper was accepted by ACM TODAES.
• 2025.07 - One paper was accepted by IEEE TCAD.
• 2025.06 - One paper was accepted by IEEE TCAS-II.

Education

• Ph.D., The University of Hong Kong (HKU)
  Electrical and Computer Engineering · 2021 – 2025
  Advisors: Prof. Ngai Wong and Prof. Can Li

• M.S., Northwestern University (NU)
  Electrical and Computer Engineering · 2019 – 2021
  Advisor: Prof. Seda Ogrenci

• B.S., Tianjin University (TJU)
  Microelectronics · 2015 – 2019
  Advisor: Prof. Yugong Wu

Industry Experience

• Zhicun (Witmem) Technology — Internship, 2025
• JD.com — Internship, 2024
• ByteDance — Internship, 2021

Interests

Beyond research, I enjoy:

• Sports — Staying active through basketball, table tennis, and badminton.
• Reading — Exploring ideas across technology, history, society, and beyond.
• Learning across disciplines — Following developments and perspectives outside my primary research areas.

Academic Service

I serve as a Technical Program Committee (TPC) member for leading conferences in electronic design automation, including DAC, DATE, ICCAD, and ASP-DAC. I also serve as a reviewer for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) and IEEE Transactions on Computers (IEEE TC).

(Last updated on Aug., 2026)